Conventional computer system architectures include three types of memory: random access memory (RAM), which is used as a work area for the operating system and applications and which is typically volatile memory; read only memory (ROM), which is used to store code that does not or should not change, such as the BIOS; and some form of non-volatile mass storage memory, such as a hard disk drive (HDD), which is used to store files, applications, etc. With the advent of FLASH memory and improvements in the reliability and lifetimes of FLASH memories, there is a trend to replace HDDs with SSDs, which have no moving parts and typically consume less power and space than their HDD counterparts. The use of SSDs allows the development of smaller and smaller computers and consumer devices, such as smart phones, handheld computers, and the like. Recent computer system architectures, however, continue to adhere to the legacy convention of maintaining a separate ROM for storing the BIOS. As used herein, the term “BIOS” refers to program code executed by a processor to perform BIOS functions, along with any data structures that may be used to store initial parameters or other information needed by the program code to perform the BIOS functions.
FIGS. 1A and 1B illustrate examples of this conventional architecture. FIG. 1A illustrates a system which includes a host processor 100 which supports two separate buses: a serial ATA (SATA) bus 102 and a low pin count (LPC) bus 104. Host 100 includes a SATA bus interface controller (SATA I/F) 106 and a low pin count (LPC) bus interface controller (LPC I/F) 108. Host 100 uses SATA I/F 106 to communicate with a mass storage device MSD 110, which is typically an HDD or SDD, via a second SATA interface controller 112. Host 100 uses LPC I/F 106 to communicate with a ROM which is used to store the BIOS (ROM BIOS) 114 via a second LPC bus interface controller 116. FIG. 1B illustrates another conventional architecture, which improves upon the architecture in FIG. 1A by replacing ROM BIOS 114 with a FLASH memory that is used to store the BIOS (FLASH BIOS) 120. FLASH BIOS 120 also uses an LPC I/F controller 116.
There are disadvantages associated with the conventional architectures described above, however. The systems illustrated in FIGS. 1A and 1B have several chips; not including additional LPC peripherals such as P1 118, these systems include at least five chips: host 100, second SATA I/F 112, HDD or SDD 110, second LPC I/F 116, and either ROM 114 or FLASH 120. Even if the second SATA I/F 112 is integrated with SDD 110 and the BIOS is integrated with its respective interface controller chip, the system has three separate chips.
There are other disadvantages associated with the conventional architectures shown in FIGS. 1A and 1B as well. The BIOS that is located in FLASH 120 cannot simply be moved into SDD 110, because SATA I/F 112 is not operable after a power-on reset: it first requires that a SATA driver be loaded from BIOS to host 100. If the BIOS was itself on a SATA device, the BIOS could not be accessed until the SATA device driver was loaded, and the SATA device driver cannot be loaded until BIOS was accessed—a circular dependency that never resolves.
Accordingly, in light of these disadvantages associated with conventional architectures, there exists a need for methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory.